Integrated circuits are formed on wafers by well-known processes and materials. These processes typically include the deposition of thin film layers by sputtering, metal-organic decomposition, chemical vapor deposition, plasma vapor deposition, and other techniques. These layers are processed by a variety of well-known etching technologies and subsequent deposition steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the wiring or metallization layer that interconnects the individual circuits. Conventional metal deposition techniques include physical vapor deposition, e.g., sputtering and evaporation, and chemical vapor deposition techniques. Some integrated circuit manufacturers are investigating electrodeposition techniques to deposit primary conductor films on semiconductor substrates.
Wiring layers have traditionally been made of aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. This technology has demanded corresponding changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies.
Copper damascene circuits are produced by initially forming trenches and other embedded features in a wafer, as needed for circuit architecture. These trenches and embedded features are formed by conventional photolithographic processes. A barrier layer, e.g., of silicon nitride, is deposited next. An initial seed or strike layer generally less than 125 nm (nanometers) thick is then deposited by a conventional vapor deposition technique, and this seed layer is typically a thin conductive layer of copper or tungsten. The seed layer is used as a base layer to conduct current for electroplating thicker films. Thinner seed layers are preferred so as to reduce overhang and closure of very small features with metal from the seed layer. The seed layer functions as the cathode of the electroplating cell as it carries electrical current between the edge of the wafer and the center of the wafer including filling of embedded structures, trenches or vias. The final electrodeposited thick film should completely fill the embedded structures, and it should have a uniform thickness across the surface of the wafer.
Generally, in electroplating processes, the thickness profile of the deposited metal is controlled to be as uniform as possible. This uniform profile is advantageous in subsequent etchback or polish removal steps, as well as uniform void-free filling of the trench structures. Prior art electroplating techniques are susceptible to thickness irregularities. Contributing factors to these irregularities are recognized to include the size and shape of the electroplating cell, electrolyte depletion effects, hot edge effects and the terminal effect.
For example, because the seed layer is initially very thin, the seed layer has a significant resistance radially from the edge to the center of the wafer. This resistance causes a corresponding potential drop from the edge where electrical contact is made to the center of the wafer. Thus, the seed layer has a nonuniform initial potential that is more negative at the edge of the wafer. The associated deposition rate tends to be greater at the wafer edge relative to the interior of the wafer. This effect is known as the “terminal effect”.
One solution to the end effect would be to deposit a thicker seed layer having less potential drop from the center of the wafer to the edge; however, thickness uniformity of the final metal layer is also impaired if the seed layer is too thick. FIG. 1 shows a prior art seed layer 100 made of copper formed atop barrier layer 102 and a dielectric wafer 104. A trench or via 106 has been cut into wafer 104. Seed layer 100 thickens in mouth region 108 with thinning towards bottom region 110. The thickness of seed layer 100 is a limiting factor on the ability of this layer to conduct electricity in the amounts that are required for electroplating operations. Thus, during electrodeposition, the relatively thick area of seed layer 100 at mouth region 108 grows more rapidly than does the relatively thin bottom region 110 with the resultant formation of a void or pocket in the area of bottom region 110 once mouth region 108 is sealed.
FIG. 2 shows an ideal seed layer 200 made of copper formed atop barrier layer 202 and a dielectric wafer 204. A trench or via 206 has been cut into wafer 204. Ideal seed layer 200 has three important properties:                1. Good uniformity in thickness and quality across the entire horizontal surface 208 of wafer 204;        2. Excellent step coverage exists in via 206 consisting of continuous conformal amounts of metal deposited onto the sidewalls; and        3. In contrast to FIG. 1, there is minimal necking in the mouth region 210.It is difficult or impossible to obtain these properties in seed layers having a thickness greater than about 120 nm to 130 nm.        
The electroplating of a thicker copper layer should begin with a layer that approximates the ideal seed layer 200 shown in FIG. 2. The electroplating process will exacerbate any problems that exist with the initial seed layer due to increased deposition rates in thicker areas that are better able to conduct electricity. The electroplating process must be properly controlled or else thickness of the layer will not be uniform, there will develop poor step coverage, and necking of embedded structures can lead to the formation of gaps of pockets in the embedded structure.
A significant part of the electroplating process is the electrofilling of embedded structures. The ability to electrofill small, high aspect ratio features without voids or seams is a function of many parameters. These parameters include the plating chemistry; the shape of the feature including the width, depth, and pattern density; local seed layer thickness; local seed layer coverage; and local plating current. Due to the requisite thinness of the seed layers to avoid necking and for other reasons as discussed above, a significant potential difference exists between the center of a wafer and the edges of a wafer. Poor sidewall coverage in embedded structures, such as trench 106 in FIG. 1, develops higher average resistivity for current traveling in a direction that is normal to the trench. Due to these factors in combination, the range of current densities in which void free filling can be obtained over the entire wafer is limited. In extreme cases (e.g., with very small features and/or thin seed layers), there is practically no set of operating conditions for filling to occur both at the wafer center and its edge.
Manufacturing demands are trending towards circumstances that operate against the goal of global electrofilling of embedded structures and thickness uniformity. Industry trends are toward thinner seed films, larger diameter wafers, increased pattern densities, and increased aspect ratio of circuit features. The trend toward thinner seed layers is required to compensate for an increased percentage of necking in smaller structures, as compared to larger ones. For example, FIG. 3 shows a comparison between etched versus seeded features for a HCM PVD process. A 45° line is drawn to show no necking, but the data shows necking as the seeded feature width rolls downward in the range from 0.3 μm to 0.15 μm.
Regarding the trend towards larger diameter wafers, it is generally understood that the deposition rate, as measured by layer thickness, can be maintained by scaling total current through the electrochemical reactor in proportion to the increased surface area of the larger wafer. Thus, a 300 mm (millimeter) wafer requires 2.25 times more current than does a 200 mm wafer. Electroplating operations are preferably performed by using a clamshell-type wafer holder that contacts the wafer only at its outer radius. Due to this mechanical arrangement, the total resistance from the edge of the wafer to the center of the wafer is proportional to the radius. Nevertheless, with the higher applied current at the edge of the larger wafer, which is required to maintain the same current density for process uniformity, the total potential drop from the edge to the center of the wafer is greater for the larger diameter wafer. This circumstance leads to an increased rate of deposition that increases with radius where deposition is measured by layer thickness. While the problem of increasing deposition rate with radius exists for all wafers, it is exacerbated in the case of larger wafers.
U.S. Pat. No. 4,469,566 issued Sep. 4, 1984 to Daniel X. Wray teaches electroplating of a paramagnetic layer with use of dual rotating masks each having aligned aperture slots. Each mask is closely aligned with a corresponding anode or cathode. The alternating field exposure provides a burst of nucleation energy followed by reduced energy for a curdling effect. The respective masks and the drive mechanism are incapable of varying the distance between each mask and its corresponding anode or cathode, and they also are incapable of varying the masked surface area of their corresponding anode or cathode.
U.S. Pat. No. 5,804,052 issued Sep. 8, 1998 to Reinhard Schneider teaches the use of rotating roller-shaped bipolar electrodes that roll without short circuit across the surface being treated in the manner of a wiper.
The foregoing discussion describes electroplating operations and focuses upon the problems that arise from thin film seed layers and the necessity of using increasingly thin seed layers. In electroplating operations, the wafer is connected and used as a cathode or the negative terminal of the electrochemical reactor. Similar problems arise in electropolishing operations where the wafer or another object is connected for use as the anode to remove rough features, e.g., from the surface of a magnetic disk for use in a computer hard drive. Portions of the film are preferentially removed in a radially outboard direction.
None of the aforementioned patents overcome the special problems related to potential drop and current density in electrochemical operations, in particular, in electroplating and electropolishing of metal thin films. There exists a need to compensate the potential drop in conductive metal films while electroplating or electropolishing these films to facilitate the production of layers having uniform thicknesses and global electrofilling of embedded features.